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revision 3.6 atp i ndustrial grade compactflash card specification atp industrial grade compactflash card specification revision 3.6 y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 1 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification disclaimer: a tp electronics inc . shall not be liable for any errors or omissions that may appear in this document, and disclaims responsibility for any consequence s resulting from the use of the information set forth herein. the information in this manual is subject to change without notice. atp general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. all parts of the atp documentation are protected by copyright law and all rights are reserved. this documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduce d to any electronic medium or machine - readable form without prior consent, in writing, from atp corporation. the information set forth in this document is considered to be ?proprietary? and ?confidential? property owned by atp. revision history date v ersion changes compared to previous issue aug.25th ,2010 2.3 - update 16gb capacity - update certification and compliance - update chs parameters - update type ii cf card information jan. 26 th,2011 3.0 - support s.m.a.r.t. command - staticdatarefresh and earlyretirement technology - update performance - update mtbf - revise density feb.25th,2011 3.1 - revise figure 4 - 1: atp s.m.a.r.t. tool operation - revise udma mode 0~4 apr .14th,2011 3.2 - add power failure protection feature sep. 30 th,2011 3.3 - preliminary spec sheet of industrial grade cf card with powerprotector feature - update new p/n and performance - update atp branch/office contact information dec.16th 2011 3.31 - official released version - revise table 3 - 19 : ultra dma data burst timing requirements - revise environment specifications jan.31st , 201 2 3.4 - add density 512mb/1gb/2gb mar.1 4 th, 2012 3.5 - add tbw (total bytes written) information - revise staticdatarefresh technology nov. 8 th, 2012 3.6 - revise table 2 - 1 system power tab le y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 2 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification table of contents 1 atp industrial grade compactflash card ov erview ................................................................. 5 1.1 atp p roduct a vailability ................................................................................................................................. 5 1.2 i ntroduction ........................................................................................................................................................ 6 1.3 m ain f eatures ...................................................................................................................................................... 6 1.4 a pplication ........................................................................................................................................................... 7 2 product specificatio n ..................................................................................................................................... 8 2.1 s ystem p ower r equirement ............................................................................................................................... 8 2.2 e nvironment s pecifications .............................................................................................................................. 8 2.3 r eliability ............................................................................................................................................................ 9 2.4 p erformance ........................................................................................................................................................ 9 2.5 chs p arameters ................................................................................................................................................ 10 2.6 e xtr a f eatures .................................................................................................................................................. 10 2.7 g lobal w ear l eveling - l onger l ife e xpectancy ........................................................................................ 11 2.8 s tatic d ata r efresh t echnology ? a ssure d ata i ntegrity ........................................................................ 11 2.9 atp p ower p rotector ? b uilt - in p ower d own d ata p rotection ............................................................... 11 2 .10 p hysical d imension s pecification ................................................................................................................... 12 2.11 m echanical f orm f actor (u nits in mm) ....................................................................................................... 12 2.12 c ertification and com pliance ......................................................................................................................... 13 2.12.1 certification table ....................................................................................................................................... 13 3 electrical interface ..................................................................................................................................... 14 3.1 p in a ssign ments and p in t ype .......................................................................................................................... 14 3.2 e lectrical d escription .................................................................................................................................... 16 3.3 e lectrical s pecification .................................................................................................................................. 24 3.3.1 input leakage current ..................................................................................................................................... 24 3.3.2 input characteristics ....................................................................................................................................... 25 3.3.3 output drive type ........................................................................................................................................... 25 3.3.4 output drive characteristics .......................................................................................................................... 26 3.3.5 attribute memory read timing ....................................................................................................................... 27 3.3.6 c onfiguration register (attribute memory) write timing specification ........................................................ 28 3.3.7 common memory read timing specification ................................................................................................. 29 3.3.8 co mmon memory write timing specification ................................................................................................. 30 3.3.9 i/o input (read) timing specification ............................................................................................................. 31 3.3.10 i/o output (write) timing specif ication .................................................................................................... 33 3.3.11 true ide pio mode read/write timing specification .............................................................................. 34 3.3.12 true ide multiword dma mode read/write timing spec ification ........................................................... 37 3.3.13 ultra dma mode read/write timing specification ................................................................................... 39 3.4 c ard c onfiguration .......................................................................................................................................... 55 3.4.1 compactflash storage card registers and memory space decoding ........................................................... 55 3.4.2 attribute memory function ............................................................................................................................. 57 3.4.3 configuration option register (base + 00h in attribute memory) ................................................................. 58 3.4.4 card configuration and status register (base + 02h in attribute memory) .................................................. 58 3.4.5 pin replacement register (base + 04h in attribute memory) ........................................................................ 58 3.4.6 socket and copy register (base + 06h in attribute memory) ......................................................................... 59 3.5 i/o t ransfer f unction ...................................................................................................................................... 60 3.6 c ommon m emory t ransfer f unction ............................................................................................................. 61 3.7 t rue ide m ode i /o t ransfer f unction ........................................................................................................... 61 3.8 h ost c onfiguration r equirements for m aster /s lave or n ew t iming m odes ......................................... 64 3.9 t ermination r esistors fo r u ltra dma o peration ...................................................................................... 64 y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 3 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 4 s . m . a . r . t . function .............................................................................................................................................. 65 4.1 s . m . a . r . t . f eature ............................................................................................................................................ 66 4.2 s . m . a . r . t . f eature r egister v alues .............................................................................................................. 66 4.3 s . m . a . r . t . d ata s tructure ............................................................................................................................. 66 4.4 atp s.m.a.r.t. t ool .......................................................................................................................................... 67 y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 4 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 1 atp industrial grade compactflash card overview 1.1 atp product availability figure 1 - 1 : atp product availability table 1 - 1: capacities atp p/n capacity af512cfi - 7acxp 512mb af1gcfi - 7acxp 1gb af2gcfi - 7acxp 2gb af4g cfi - 7acxp 4gb af8gcfi - 7abxp 8gb af16gcfi - 7abxp 16gb af32gcfi - 7aaxp 32gb *note : ? p ? stands for powerprotector feature y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 5 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 1.2 introduction by utilizing slc nand flash memory and advanced global wear leveling technology, the atp industrial grade compact flash card has enhanced endurance levels and a longer product lifespan. the atp industrial grade cf card implements the staticdatarefresh technology, which monitors the error bit levels during each read operation to ensure data integrity, and the earlyreti rement technology prevents data loss from weak blocks. the atp industrial grade cf card has also incorporated the s.m.a.r.t. (self - monitoring, analysis, and reporting technology) function which monitors various parameters of endurance and reliability, ind icating activity that is out of the normal range. this information helps predict storage failure for preventative action. patent atp powerprotector technology is implemented in atp industrial grade cf card to ensu re a sufficient amount of backup power dur ing power abnormalities to minimize the risk of data loss or firmware corruption. 1.3 main feature s ? host interface: compliance with cf specification 4.1 pre - screened single level cell (slc) nand flash memory true ide mode compatible: support p io mode 0 ~6, mdma mode 0~2, udma mode 0~ 4 ? high performance: sequential read up to 51 mbyte/s (udma 4 , flash number x 2 ) sequential write up to 25 mbyte/s (udma 4 , flash number x 2 ) capacity: 512m b to 32gb ? industrial grade temp. : - 40 o c to 85 o c ? end urance: enhanced endurance by global wear leveling and bad block management 13/24 bit bch - ecc engines can correct up to 24 bit errors per 1,024 byte data mtbf > 5,000,000 hours (@2 5 o c ) data reliability: bit error rate 10e - 15 (nand flash) y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 6 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification number of connecto r insertion/removals: >10,000 ? staticdatarefresh technology to assure data integrity in read operations. ? powerprotector, built - in power - down data protection ? s.m.a.r.t. function support for life time monito r ? power saving mode (automatic sleep and wake - up m echanism) 1.4 application atp industrial grade cf cards are designed for demanding industrial applications, such as military/ aerospace , autom ation , marine navigation, embedded systems, tele commun ication equipment or networking and medical equipment where mi ssion - critical data requires the highest level of reliability, durability, and data integrity. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 7 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 2 product specification 2.1 system power requirement table2 - 1: system power table voltage maximum average rms current measurement method 3.3v +/ - 5% 75ma (500ma in power level 1) 3.3v at 25 oc 5.0v +/ - 10% 100ma (500ma in power level 1) 5.0v at 25 oc 2.2 environment specifications table2 - 2 : environment specifications type standard temperature operating - 40 oc to 85 oc non - operating - 40oc t o 85oc humidity storage 40 oc , 93% rh / 500hrs 85oc,85%rh / 500hrs random vibration test non - operating 10~2000hz, 6grms, 30min per axis drop test non - operating 150cm/free fall uv light exposure test (iso 7816 - 1) non - operating 254nm, 15ws/cm2 y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 8 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 2.3 reliability table 2 - 3 : reliability type measurement number of insertions 1 0,000 minimum endurance 100,000 p/e cycles slc nand flash cell endurance tbw (total bytes written) 512mb 10 terabyte random write 1gb 20 terabyte random write 2gb 40 ter abyte random write 4gb 80 terabyte random write 8gb 160 terabyte random write 16gb 320 terabyte random write 32gb 640 terabyte random write mtbf (@ 2 5 o c ) > 5 ,000,000 hours note: endurance for flash cards can be predicted based on the usage conditi ons applied to the device, the internal nand flash cycles, the write amplification factor, and the wear l eveling efficiency of the flash devices. 2.4 performance table 2 - 4 : performance model p/n seq . read ( k b/s) seq . write ( k b/s) random read (kb/s) random write (kb/s) af512cfi - 7acxp 24945 10742 24265 3408 af1gcfi - 7acxp 29446 15597 28464 5200 af2gcfi - 7acxp 30476 16075 29090 5624 af4gcfi - 7acxp 50319 19266 44377 6285 af8gcfi - 7abxp 51328 24945 44377 7261 af16gcfi - 7abxp 51328 25190 44377 7402 af32gcfi - 7aa xp 50381 24945 43620 7553 note: tested by hdbench 3.40 beta6 with 40mb file size. the performance may vary based on different testing environments. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 9 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 2.5 chs parameters table 2 - 5 chs table sm2232ad with slc product density flash type cylinders heads se ctors total sectors physical capacity 512mb 2k page 991 16 63 998928 511451136 1gb 2k page 1966 16 63 1981728 1014644736 2gb 2k page 3900 16 63 3931200 2012774400 4gb 8k page 7785 16 63 7847280 4017807360 8gb 8k page 15538 16 63 15662304 8019099648 1 6gb 8k page 31045 16 63 31293360 16022200320 32gb 8k page 62041 16 63 62537328 32019111936 2.6 extr a features table 2 - 6 : extra features type measurement esd proof yes rohs compliant yes esd proof iec 61000 - 4 - 2: non- contact pad (coupling plane dischar ge) +/ - 8kv, non - contact pad (air discharge) +/ - 15kv y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 10 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 2.7 global wear leveling - longer life expectancy the program / erase cycle of each sector/page/block is finite. writing constantly on the same spot will cause the flash to wear out quickly. furt hermore, bit errors are not proportioned to p/e cycles; sudden death may occur when the block is close to its p/e cycle limit. then unrecoverable bit errors will cause fatal data loss (especially for system data or fat). global wear leveling algorithm ev enly distributes the p/e cycles of each block to minimize the possibility of one block exceeding its max p/e cycles before the rest. in return, the life expectancy of memory storage device is prolonged and the chance/occurrence of unrecoverable bit errors could be reduced. 2.8 staticd atarefresh technology ? assure d ata integrity over time the error bits accumulate to the threshold in the flash memory cell and eventually become uncorrectable despite using the ecc engine. in the traditional handling method, the data is moved to a different location in the flash memory; despite the corrupted data is beyond repair ed before the transition. to pre vent data corruption, the cf card monitors the error bit levels in each read operation; when it reaches the preset thres hold value, staticdatarefresh is achieved by erasing and re - prog ramming the data into the same block or into another block . after the re - programming operation is completed, the controller reads the data and compares the data/parity to ensure data integrity . 2.9 atp powerprotector ? built - in power down data protection atp powerprotector technology ensures a sufficient amount of reserve power during any power abnormalities such as unstable voltages and power outages. powerprotector? s patent pending technolo gy is a stand alone hardware design that does not require specific controllers or customized firmware. this feature provides greater flexibility during the design of a smaller form factor such as compactflash cards . d uring a sudden power failure, t he dri ve then draws power from powerprotector?s solid state capacitors for reserve power, which guarantee reliable drive operations. the solid state capacitors allow the flash to finish processing the last command or data. supercap , the traditional power prote ction design, is well known for its sensitivity to temperature change and has a tendency of losing its capacitance and functionality at extreme temperatures. the average life span of supercap is less than two years; the capacitance will degrade over time a nd eventually fail to perform. atp powerprotector surpasses the natural limitations of supercap designs by support ing wide y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 11 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification temperature and an average life span of over five years without capacitance degradation . powerprotector offers an advanced level of protection ensuring that data integrity is not compromised during a power failure scenario, and preserves critical data in mission critical applications. 2.10 physical dimension specification table 2 - 7 : physical specifications type measurement type i leng th 36.4mm 0.15mm width 42.8mm 0.10mm thickness 3.3 mm 0.10mm weight 9.0 g typical type ii length 36.4mm 0.15mm width 42.8mm 0.10mm thickness 5.0 mmmax weight 9.0 g typical 2.11 mechanical form f actor (unit s in mm) figure 2 - 1: atp comp actflash c ard physical dimensions type i y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 12 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification type ii 2.12 certification and compliance 2.12.1 certification table table 2 - 8 : certification table mark/approval doc u mentation certification the ce marking (also known as ce m ark) is a mandatory conformance mark on many products placed on the single market in the european economic area (eea). the ce marking certifies that a product has met eu consumer safety, health or environmental requirements. ce stands for conformit europenne, "european conformity" in french. yes fcc part 15 class b was used for evolution of united states (us) emission standards for commercial electronic products, the united states (us) covers all types of unintentional radiators u nder subparts a and b (sections 15.1 through 15.199) of fcc 47 cfr part 15, usually called just fcc part 15 yes rohs is t he acronym for restriction of hazardous substances. rohs, also known as directive 2002/95/ec, originated in the european union and restricts the use of specific hazardous materials found in electrical and electronic products. all applicable products in the eu market after july 1, 2006 must pass rohs compliance. for the complete directive, see directive 2002/95/ec of the european parliament . yes y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 13 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3 e lectrical i nterface 3.1 pin assignments and pin type the host is connected to the compactflash card using a standard 50 - pin connector. the connector in the host consists of two rows of 25 male contacts each on 50 mil (1.27 mm) centers. the signal/pin a ssignme nts are listed in table 3- 1 . low active signals have a ?- ? prefix. pin types are input, output or input/output. section 3 .3 defines the dc characteristics for all input and output type structures. table 3 - 1: pin assignments and pin type pc card memory m ode pc card i/o mode true ide mode 13 pin signal name pin type in, out type pin signal name pin type in, out type pin signal name pin type in, out type 1 gnd ground 1 gnd ground 1 gnd ground 2 d03 groun d i1 z,oz 3 2 d03 i/o i1z , oz 3 2 d03 i/o i1z , oz3 3 d04 i/o i 1 z,oz 3 d04 i/o i1z , oz 3 d04 i/o i1z , oz3 4 d05 i/o i1 z,oz 4 d05 i/o i1z , oz 4 d05 i/o i1z , oz3 5 d06 i/o i 1 z,oz 5 d06 i/o i1z , oz 5 d06 i/o i1z , oz3 6 d07 i/o i 1 z,oz 6 d07 i/o i1z , oz 6 d07 i/o i1z , oz3 7 ?ce1 ?ce1 ?c ?oe ?oe ?ata sel ?iois16 o ot 3 24 ?iois16 o on3 pc card memory mode pc card i/o mode true ide mode 13 pin signal name pin type in, out type pin signal name pin type in, out type pin signal name pin type in, out type y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 14 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 25 ?cd2 ?cd2 ?cd2 ?cd1 ?cd1 ?cd1 ?ce2 1 i i3u 32 ?ce2 1 i i3u 32 ?cs1 1 i i3 z 33 ?vs1 o ground 33 ?vs1 o ground 33 ?vs1 o ground 34 - iord hstrobe 9 hdmardy 1 0 i i3 u 34 - iord hstrobe 9 hdmar dy 1 0 i i3 u 34 - iord 6 hstrobe 7 hdmardy 8 i i3z 35 ?iowr i i3 u 35 ?iowr ?iowr 6 stop 7,8 i i3z 36 ?we i i3 u 36 ?we i i3 u 36 ?we 3 i i3 u 37 r eady o ot1 37 ?ireq ?cse ?csel ?csel ?vs2 o open 40 ?vs2 o open 40 ?vs2 o open 41 reset i i2z 41 reset i i2z 41 ?reset 2z 42 ?wait ? ddmardy 9 dstrobe 10 o ot1 42 ?wait ? ddmardy 9 dstrobe 10 o ot1 42 iordy 6 ? ddmardy 7 dstrobe 8 o on1 ot1 1 2 43 ?inpack ? o ot1 43 ?inpack ? o oz 1 44 ?reg ? ?reg ? ? dmack 5 i i3u 45 bvd2 o ot1 45 ?spkr ?dasp ?stschg ?pdiag note s : 1) these signals are required o nly for 16 bit accesses and not required when installed in 8 bit systems. devices should allow for 3 - state signals not to consume current. 2) the signal should be grounded by the host. 3) the signal should be tied to vcc by the host. 4) the - csel signal is ignored by the card in pc card modes. however, because it is not pulled up on the card in these modes, it should not be left floating by the host in pc card modes. in these modes, the pin should be connected by the host to pc card a25 or grounded by the h ost. 5) if dma operations are not used, the signal should be held high or tied to vcc by the host. for proper operation in older hosts: while dma operations are not active, the card shall ignore this signal, including a floating condition 6) signal usage i n true ide mode except when ultra dma mode protocol is active. 7) signal usage in true ide mode when ultra dma mode protocol dma write is active. 8) signal usage in true ide mode when ultra dma mode protocol dma read is active. 9) signal usage in pc card i /o and memory mode when ultra dma mode protocol dma write is active. 10) signal usage in pc card i/o and memory mode when ultra dma mode protocol dma read is active. 11) signal usage in pc card i/o and memory mode when ultra dma protocol is active. 12) sig nal is a totem - pole output during ultra dma data bursts in true ide mode. 13) the mode is optional for cf+ cards, but required for compactflash storage cards. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 15 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.2 electrical description the compactflash card functions in three basic modes: 1) pc card ata using i/o mode 2) pc card ata using memory mode y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 16 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3) true ide mode, which is compatible with most disk drives. atp industrial compactflash card supports all three modes. the configuration of the compactflash card is co ntrolled using the standard pcmcia configuration registers starting at address 200h in the attribute memory space of the storage card or for true ide mode, pin 9 being grounded. table 3 - 2: signal description signal name dir. pin description a10 - a0 (pc card memory mode) i 8,10,11,12, 14,15,16,17, 18,19,20 these address lines along with the - reg signal are used to select the following: the i/o port address registers within the compactflash card, the memory mapped port address registers within the c ompactflash card, a byte in the card's information structure and its configuration control and status registers. a10 - a0 (pc card i/o mode) this signal is the same as the pc card memory mode signal. a2 - a0 (true ide mode) 18,19,20 in t rue ide mode, only a[2:0] are used to select the one of eight registers in the task file, the remaining address lines should be grounded by the host. bvd1 (pc card memory mode) - stschg (pc card i/o mode) status changed - pdiag (true ide mode) i/o 46 this signal is asserted high, as bvd1 is not supported. this signal is asserted low to alert the host to changes in the ready and write protect states, while the i/o interface is configured. its use is controlled by the card config and status regist er. in the true ide mode, this input / output is the pass diagnostic signal in the master / slave handshake protocol. bvd2 (pc card memory mode) - spkr (pc card i/o mode) i/o 45 this signal is asserted high, as bvd2 is not supported. this lin e is the binary audio output from the card. if the card does not support the binary audio function, this line should be held negated. - cd1, - cd2 (pc card memory mode) o 26,25 these card detect pins are connected to ground on the compactflash card. th ey are used by the host to determine that the compactflash card is fully inserted into its socket. signal name dir. pin description y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 17 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification - ce1, - ce2 (pc card memory mode) card enable - ce1, - ce2 (pc card i/o mode) card enable i 7,32 these input si gnals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. - ce2 always accesses the odd byte of the word. - ce1 accesses the even byte or the odd byte of the word depending on a0 and - ce2. a mul tiplexing scheme based on a0, - ce1, - ce2 allows 8 bit hosts to access all data on d0 - d7. this signal is the same as the pc card memory mode signal. - cs0, - cs1 (true ide mode) in the true ide mode, - cs0 is the chip select for the task file registers while - cs1 is used to select the alternate status register and the device control register. while ? dmack is asserted, - cs0 and ? cs1 shall be held negated and the width of the transfers shall be 16 bits. - csel (pc card memory mode) - csel (pc card i/ o mode) - csel (true ide mode) i 39 this signal is not used for this mode, but should be connected by the host to pc card a25 or grounded by the host. this signal is not used for this mode, but should be connected by the host to pc card a25 or groun ded by the host. this internally pulled up signal is used to configure this device as a master or a slave when configured in the true ide mode. when this pin is grounded, this device is configured as a master. when the pin is open, this device is configu red as a slave. d15 - d00 (pc card memory mode) i/o 31,30,29,28, 27,49,48,47, 6,5,4,3,2, 23, 22, 21 these lines carry the data, commands and status information between the host and the controller. d00 is the lsb of the even byte of the word. d08 is t he lsb of the odd byte of the word. d15 - d00 (pc card i/o mode) this signal is the same as the pc card memory mode signal. d15 - d00 (true ide mode) in true ide mode, all task file operations occur in byte mode on the low order bus d[7:0] wh ile all data transfers are 16 bit using d[15:0]. gnd (pc card memory mode) gnd (pc card i/o mode) gnd (true ide mode) -- 1,50 ground. this signal is the same for all modes. this signal is the same for all modes. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 18 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification signal n ame dir. pin description - inpack (pc card memory mode) - inpack (pc card i/o mode) input acknowledge dmarq (true ide mode) o 43 this signal is not used in this mode. the input acknowledge signal is asserted by the compactflash storage c ard when the card is selected and responding to an i/o read cycle at the address that is on the address bus. this signal is used by the host to control the enable of any input data buffers between the compactflash storage card and the cpu. hosts that suppo rt a single socket per interface logic, such as for advanced timing modes and ultra dma operation may ignore the ? inpack signal from the device and manage their input buffers based solely on card enable signals. this signal is a dma request that is used f or dma data transfers between host and device. it shall be asserted by the device when it is ready to transfer data to or from the host. for multiword dma transfers, the direction of data transfer is controlled by - iord and - iowr. this signal is used in a handshake manner with ( - )dmack, in pcmcia i/o mode, the - dmarq shall be ignored by the host while the host is performing an i/o read cycle to the device. the host shall not initiate an i/o read cycle while - dmarq is asserted by the device. in true ide m ode, dmarq shall not be driven when the device is not selected in the drive - head register. while a dma operation is in progress, - cs0 (- ce1)and - cs1 (- ce2) shall be held negated and the width of the transfers shall be 16 bits. if there is no hardware sup port for true ide dma mode in the host, this output signal is not used and should not be connected at the host. in this case, the bios must report that dma mode is not supported by the host so that device drivers will not attempt dma mode operation. a hos t that does not support dma mode and implements both pc card and true ide modes of operation need not alter the pc card mode connections while in true ide mode as long as this does not prevent proper operation in any mode. is not selected in the drive - head register. while a dma operation is in progress, - cs0 (- ce1)and - cs1 (- ce2) shall be held negated and the width of the transfers shall be 16 bits. signal name dir. pin description y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 19 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification - iord (pc card memory mode except ultra dma protocol act ive) i 34 this signal is not used in this mode. this is an i/o read strobe generated by the host. this signal gates i/o data onto the bus from the compactflash storage card when the card is configured to use the i/o interface. in true ide mode, while ultra dma mode is not active, this signal has the same function as in pc card i/o mode. in all modes when ultra dma mode dma read is active, this signal is asserted by the host to indicate that the host is ready to receive ultra dma data - in burst s. the host may negate ? hdmardy to pause an ultra dma transfer. in all modes when ultra dma mode dma write is active, this signal is the data out strobe generated by the host. both the rising and falling edge of hstrobe cause data to be latched by the device. the host may stop generating hstrobe edges to pause an ultra dma data - out burst. - iord (pc card i/o mode except ultra dma protocol active) - iord (true ide mode ? except ultra dma protocol active) - hdmardy (all modes - ultra dma protocol d ma read) hstrobe (all modes - ultra dma protocol dma write) - iowr (pc card memory mode ? except ultra dma protocol active) - iowr (pc card i/o mode ? except ultra dma protocol active) - iowr (true ide mode ? except ultra dma protocol active) stop ( all modes ? ultra dma protocol active) i 35 this signal is not used in this mode. the i/o write strobe pulse is used to clock i/o data on the card data bus into the compactflash storage card controller registers when the compactflash storage card is configured to use the i/o interface. the clocking shall occur on the negative to positive edge of the signal (trailing edge). in true ide mode, while ultra dma mode protocol is not active, this signal has the same function as in pc card i/o mode. when ul tra dma mode protocol is supported, this signal must be negated before entering ultra dma mode protocol. in all modes, while ultra dma mode protocol is active, the assertion of this signal causes the termination of the ultra dma data burst . y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 20 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification signal na me dir. pin description - oe (pc card memory mode) - oe (pc card i/o mode) - ata sel (true ide mode) i 9 this is an output enable strobe generated by the host interface. it is used to read data from the compactflash card in memory mode and to read the cis and configuration registers. in pc card i/o mode, this signal is used to read the cis and configuration registers. to enable true ide mode this input should be grounded by the host. ready (pc card memory mode) o 37 in memory mode, this s ignal is set high when the compactflash card is ready to accept a new data transfer operation and is held low when the card is busy. at power up and at reset, the ready signal is held low (busy) until the compactflash card has completed its power up o r reset function. no access of any type should be made to the compactflash card during this time. note, however, that when a card is powered up and used with reset continuously disconnected or asserted, the reset function of the reset pin is disabled. consequently, the continuous assertion of reset from the application of power shall not cause the ready signal to remain continuously in the busy state. - ireq (pc card i/o mode) i/o operation ? after the compactflash card has been configured for i/o operation, this signal is used as - interrupt request. this line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. intrq (true ide mode) in true ide mode signal is the active high interrupt request to the host. - reg (pc card memory mode ? except ultra dma protocol active) attribute memory select - reg (pc card i/o mode ? except ultra dma protocol active) - dmack (pc card memory mode when ultra dma protocol active) dmack (pc card i/o mode when ultra dma p rotocol active) - dmack (true ide mode) i 44 this signal is used during memory cycles to distinguish between common memory and register (attribute) memory accesses. high for common memory, low for attribute memory. in pc card memory mode, when ultra dma protocol is supported by the host and the host has enabled ultra dma protocol on the card the, host shall keep the - reg signal negated during the execution of any dma command by the device the signal shall also be active (low) during i/o cycles when the i /o address is on the bus. in pc card i/o mode, when ultra dma protocol is supported by the host and the host has enabled ultra dma protocol on the card the, host shall keep the - reg signal asserted during the execution of any dma command by the device. th is is a dma acknowledge signal that is asserted by the host in response to ( - )dmarq to initiate dma transfers. in true ide mode, while dma operations are not active, the card shall ignore the ( - )dmack signal, including a floating condition. if dma operatio n is not supported by a true ide mode only host, this signal should be driven high or connected to vcc by the host. a host that does not support dma mode and implements both pc card and true - ide modes of operation need not alter the pc card mode connection s while in true - ide mode as long as this does not prevent proper operation all modes. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 21 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification signal name dir. pin description reset (pc card memory mode) reset (pc card i/o mode) - reset (true ide mode) i 41 the compactflash card is reset wh en the reset pin is high with the following important exception: the host may leave the reset pin open or keep it continually high from the application of power without causing a continuous reset of the card. under either of these conditions, the card sh all emerge from power - up having completed an initial reset. the compactflash card is also reset when the soft reset bit in the card configuration option register is set. this signal is the same as the pc card memory mode signal. in the true ide mode , this input pin is the active low hardware reset from the host. vcc (pc card memory mode) -- 13,38 +5 v, +3.3 v power. vcc (pc card i/o mode) vcc (true ide mode) this signal is the same for all modes. this signal is the same for all modes . - vs1 - vs2 (pc card memory mode) o 33 40 voltage sense signals. - vs1 is grounded on the card and sensed by the host so that the compactflash card cis can be read at 3.3 volts and - vs2 is reserved by pcmcia for a secondary voltage and is not connect ed on the card. - vs1 - vs2 (pc card i/o mode) - vs1 - vs2 (true ide mode) this signal is the same for all modes. this signal is the same for all modes. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 22 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification signal name dir. pin description - wait (pc card memory mode C except ultra dma protoco l active) - wait (pc card i/o mode ? except ultra dma protocol active) iordy (true ide mode ? except ultra dma protocol active) - ddmardy (all modes ? ultra dma write protocol active) dstrobe (all modes ? ultra dma read protocol active) o 42 the - wait signal is driven low by the compactflash storage card to signal the host to delay completion of a memory or i/o cycle that is in progress. this signal is the same as the pc card memory mode signal. in true ide mode, except in ultra dma modes, this o utput signal may be used as iordy. in all modes, when ultra dma mode dma write is active, this signal is asserted by the device during a data burst to indicate that the device is ready to receive ultra dma data out bursts. the device may negate - ddmardy to pause an ultra dma transfer. in all modes, when ultra dma mode dma read is active, this signal is the data in strobe generated by the device. both the rising and falling edge of dstrobe cause data to be latched by the host. the device may stop generat ing dstrobe edges to pause an ultra dma data in burst. - we (pc card memory mode) i 36 this is a signal driven by the host and used for strobing memory write data to the registers of the compactflash card when the card is configured in the memory inter face mode. it is also used for writing the configuration registers. - we (pc card i/o mode) in pc card i/o mode, this signal is used for writing the configuration registers. - we (true ide mode) in true ide mode, this input signal is not used and should be connected to vcc by the host. wp (pc card memory mode) write protect - iois16 (pc card i/o mode) - iocs16 (true ide mode) o 24 memory mode ? the compactflash card does not have a write protect switch. this signal is held low after th e completion of the reset initialization sequence. i/o operation ? when the compactflash card is configured for i/o operation pin 24 is used for the - i/o selected is 16 bit port ( - iois16) function. a low signal indicates that a 16 bit or odd byte only op eration can be performed at the addressed port. in true ide mode this output signal is asserted low when this device is expecting a word data transfer cycle. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 23 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3 electrical specification the following tables define all d.c. characteris tics for the atp industrial grade compactflash card series. unless otherwise stated, conditions are: vcc = 5v 10% vcc = 3.3v 10% table 3 - 3: absolute maximum conditions parameter symbol conditions input power vcc - 0.3v min. to 6.5v max. voltage on a ny pin except vcc with respect to gnd. v - 0.5v min. to vcc + 0.5v max. 3.3.1 input leakage current note: in table 3- 4 below, x refers to the characteristics. for example, i1u indicates a pull - up resistor with a type 1 input characteristic. table 3 - 4: input leakage current type parameter symbol conditions min typ max units ixz input leakage current il vih = vcc / vil = gnd - 1 1 a ixu pull - up resistor rpu1 vcc = 5.0v 50k 500k ohm ixd pull - down resistor rpd1 vcc = 5.0v 50k 500k ohm note: the minimum pull - up resistor leakage current meets the pcmcia specification of 10k ohms but is intentionally higher in the compactflash specification to reduce power use. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 24 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.2 input characteristics table 3 - 5: input characteristics ty pe parameter symbol min typ max min typ max units vcc = 3.3 v vcc = 5.0 v 1 input voltage cmos vih vil 2.4 0.6 4.0 1 0.8 volts 2 input voltage cmos vih vil 1.5 0.6 2.0 0.8 volts 3 input voltage cmos schmitt trigger vth vtl 1.8 1.0 2.8 2.0 volts notes: per pcmcia electrical specification signal interface note 1, the host provides a logic output high voltage for a cmos load of .9 x vcc. for a 5 volt product, this translates to .9 x 4.5 = 4.05 volts minim um voh. in udma modes greater than 4, the following characteristics apply. voltage output high and low values shall be met at the source connector to include the effect of series termination. table 3 - 6 : input characteristics (udma mode > 4) parameter sym bol min max units dc supply voltage to receivers v dd3 3.3 - 8% 3.3 + 8% volts low to high input threshold v+ 1.5 2.0 volts high to low input threshold v? 1.0 1.5 volts difference between input thresholds: v hy s 320 mv ((v+current value) ? (v?current value)) average of thresholds: ((v+current value) + (v?current value))/2 v thrav g 1.3 1.7 volts note: in table 3 - 7 below, x refers to the characteristics. for example, ot3 refers to totem pole output with a type 3 output dri ve characteristic. 3.3.3 output drive type table 3 - 7 : output drive type type output type valid conditions otx totempole ioh & iol ozx tri - state n - p channel ioh & iol opx p - channel only ioh only onx n - channel only iol only y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 25 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.4 output drive ch aracteristics table 3 - 8 : output drive characteristics type parameter symbol conditions min typ max units 1 output voltage voh vol ioh = - 4 ma iol = 4 ma vcc - 0.8v gnd +0.4v volts 2 output voltage voh vol ioh = - 4 ma iol = 4 ma vcc - 0.8v gnd +0.4v volts 3 output voltage voh vol ioh = - 4 ma iol = 4 ma vcc - 0.8v gnd +0.4v volts x tri - state leakage current ioz vol = gnd voh = vcc - 10 10 a in udma modes greater than 4, the characteristics specified in the fol lowing table apply. voltage output high and low values shall be met at the source connector to include the effect of series termination. table 3 - 9 : output drive (udma mode > 4) parameter symbol min max units dc supply voltage to drivers v dd3 3.3 - 8% 3.3 + 8% volts voltage output high at - 6 ma to +3 ma (at voh2 the output shall be able t o supply and sink current to vdd3) v oh2 v dd3 - 0.51 v dd3 + 0.3 volts voltage output low at 6 ma v ol2 0.51 volts notes: 1) ioldasp shall be 12 ma mini mum to meet legacy timing and signal integrity. 2) ioh value at 400 a is insufficient in the case of dmarq that is pulled low by a 5.6 k resistor. 3) voltage output high and low values shall be met at the source connector to include the effect of series termination. 4) a device shall have less than 64 a of leakage current into a 6.2 k pull - down resistor while the intrq signal is in the released state. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 26 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.5 attribute memory read timing attribute memory access time is defined as 300 ns. detailed t iming specs are shown in table 3- 10. table 3 - 10: attribute memory read timing speed version 300 ns item symbol ieee symbol min ns . max ns . read cycle time tc(r) tavav 300 address access time ta(a) tavqv 300 card enable access time ta(ce) telqv 300 output enable access time ta(oe) tglqv 150 output disable time from ce tdis(ce) tehqz 100 output disable time from oe tdis(oe) tghqz 100 address setup time tsu (a) tavgl 30 output enable time from ce ten(ce) telqnz 5 output enable time from oe ten(oe) tglqnz 5 data valid from address change tv(a) taxqx 0 figure 3 - 1 : attribute memory read timing diagram y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 27 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.6 configuration register (attribute memory) write timing specification table 3 - 11: conf iguration register (attribute memory) write timing speed version 250 ns item symbol ieee symbol min ns max ns write cycle time tc(w) tavav 250 write pulse width tw(we) twlwh 150 address setup time tsu(a) tavwl 30 write recover y time trec(we) twmax 30 data setup time for we tsu(d - weh) tdvwh 80 data hold time th(d) twmdx 30 figure 3 - 2 : configuration register (attribute memory) write timing diagram y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 28 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.7 common memory read timing specification table 3 - 12: com mon memory read timing cycle time mode: 250 ns 120 ns 100 ns 80 ns item symbol ieee symbol min ns . max ns. min ns . max ns . min ns . max ns . min ns . max ns . output enable access time ta(oe) tglqv 125 60 50 45 output disable tim e from oe tdis(oe) tghqz 100 60 50 45 address setup time tsu(a) tavgl 30 15 10 10 address hold time th(a) tghax 20 15 15 10 ce setup before oe tsu(ce) telgl 0 0 0 0 ce hold following oe th(ce) tgheh 20 1 5 15 10 wait delay falling from oe tv(wt - oe) tglwtv 35 35 35 na 1 data setup for wait release tv(wt) tqvwth 0 0 0 na 1 wait width time 2 tw(wt) twtlwth 350 350 350 na 1 notes: 1) ? wait is not supported in this mode. 2 ) the maximum load on - wait is 1 lsttl with 50 pf (40pf below 120nsec cycle time) total load. all times are in nanoseconds. dout signifies data provided by the compactflash card to the system. the - wait signal may be ignored if the - oe cycle to cycle time is greater than the wait width time. the max wait width time can be determined from the card information s tructure. the wait width time meets the pcmcia specification of 12s but is intentionally less in this specification. figure 3 - 3 : common memory read timing diagram y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 29 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.8 common memory write timing specification table 3 - 1 3 : common memory write timing cycle ti me mode: 250 ns 120 ns 100 ns 80 ns item symbol ieee symbol min ns . max ns . min ns . max ns . min ns . max ns . min ns . max ns . data setup before we tsu (d - weh) tdvwh 80 50 40 30 data hold following we th(d) twmdx 30 15 10 10 we pulse width tw(we) twlwh 150 70 60 55 address setup time tsu(a) tavwl 30 15 10 10 ce setup before we tsu(ce) telwl 0 0 0 0 write recovery time trec(we) twmax 30 15 15 15 address hold time th(a) t ghax 20 15 15 15 ce hold following we th(ce) tgheh 20 15 15 10 cycle time mode: 250 ns 120 ns 100 ns 80 ns item symbol ieee symbol min ns . max ns . min ns . max ns . min ns . max ns . min ns . max ns . wait delay falling from w e tv (wt - we) twlwtv 35 35 35 na 1 we high from wait release tv(wt) twthwh 0 0 0 na 1 wait width time 2 tw (wt) twtlwth 350 350 350 na 2` notes: 1) ? wait is not supported in this mode. 2) the maximum load on - wait is 1 lstt l with 50 pf (40pf below 120nsec cycle time) total load. all times are in nanoseconds. din signifies data provided by the system to the compactflash card. the - wait signal may be ignored if the - we cycle to cycle time is greater than the wait width time. t he max wait width time can be determined from the card information structure. the wait width time meets the pcmcia specification of 12s but is intentionally less in this specification. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 30 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification figure 3 - 4 : common memory write timing 3.3.9 i/o input (read) timing specification table 3 - 1 4 : i/o read timing cycle time mode: 250 ns 120 ns 100 ns 80 ns item symbol ieee symbol min ns . max ns . min ns . max ns . min ns . max ns . min ns . max ns . data delay after iord td(iord) tlglqv 100 50 50 45 data hold following iord th(iord) tlghqx 0 5 5 5 iord width time tw (iord) tlgligh 165 70 65 55 address setup before iord tsua(iord) tavigl 70 25 25 15 address hold following iord tha(iord) tlghax 20 10 10 10 ce setup before iord tsuce(iord) teligl 5 5 5 5 ce hold thce(iord) tlgheh 20 10 10 10 y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 31 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification following io rd reg setup before iord tsureg (iord) trgligl 5 5 5 5 reg hold following iord threg (iord) tlghrgh 0 0 0 0 inpack delay falling from iord 3 tdfinpack (iord) tlglial 0 45 0 na1 0 na1 0 na1 inpack delay rising from iord 3 tdrinpack (iord) tlghiah 45 na 1 na 1 na 1 iois16 delay falling from address 3 tdfiois16 (adr) tavisl 35 na 1 na 1 na 1 iois16 delay rising from address 3 tdriois16 (adr) tavish 35 na 1 na 1 na 1 wait delay falling from iord 3 tdwt(iord) tlglwtl 35 35 35 na 2 data delay from wait rising 3 td(wt) twthqv 0 0 0 na 2 wait width time 3 tw(wt) twtlwth 350 350 350 na 2 notes: 1) - iois16 and - inpack are not supported in this m ode. 2) - wait is not supported in this mode. 3) maximum load on - wait, - inpack and - iois16 is 1 lsttl with 50 pf (40pf below 120nsec cycle time) total load. all times are in nanoseconds. minimum time from - wait high to - iord high is 0 nsec, but minimum - io rd width shall still be met. dout signifies data provided by the compactflash card to the system. wait width time meets pcmcia specification of 12s but is intentionally less in this spec. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 32 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification figure 3 - 5 : i/o read timing diagram 3.3.10 i/o output (write) timing specification table 3 - 1 5 : i/o write timing cycle time mode: 255 ns 120 ns 100 ns 80 ns item symbol ieee symbol min ns . max ns. min ns. max ns. min ns. max ns. min ns . max ns. data setup before iowr tsu(iowr) tdviwh 60 20 20 15 data hold following iowr th(iowr) tlwhdx 30 10 5 5 iowr width time tw(iowr) tlwliwh 165 70 65 55 address setup before iowr tsua(iowr) taviwl 70 25 25 15 address hold following iowr tha(iowr) tlwhax 20 20 10 10 ce setup before iowr tsuce (iowr) teliwl 5 5 5 5 ce hold following iowr thce (iowr) tlwheh 20 20 10 10 reg setup before iowr tsureg (iowr) trgliwl 5 5 5 5 reg hold following iowr threg (iowr) tlwhrgh 0 0 0 0 iois16 delay falling from address3 tdfiois16 (adr) tavisl 35 na1 na1 na1 iois16 delay rising from address3 tdriois16 (adr) tavish 35 na1 na1 na1 wait delay falling from iowr3 tdwt(iowr) tlwlwtl 35 35 35 na2 iowr high f rom wait high3 tdriowr (wt) twtjiwh 0 0 0 na2 wait width time3 tw(wt) twtlwth 350 350 350 na2 notes: 1) - iois16 and - inpack are not supported in this mode. 2) - wait is not supported in this mode. 3) the maximum load on - wait, - inpac k, and - iois16 is 1 lsttl with 50 pf (40pf below 120nsec cycle time) total load. all times are in nanoseconds. minimum time from - wait high to - iowr high is 0 nsec, but minimum - iowr width shall still be met. din signifies data provided by the system to th e compactflash card. the wait width time meets the pcmcia specification of 12 s but is intentionally less in this specification. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 33 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification f igure 3 - 6 : i/o write timing diagram 3.3.11 true ide pio mode read/write timing specification the timing diagram for true id e mode of operation in this section is drawn using the conventions in the ata - 4 specification, which are different than the conventions used in the pcmcia specification and earlier versions of this specification. signals are shown with their asserted state as high regardless of whether the signal is actually negative or positive true. consequently, the - iord, the - iowr and the - iocs16 signals are shown in the diagram inverted from their electrical states on the bus. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 34 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification table 3 - 1 6 : true ide pio mode read/wri te timing item mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 note t0 cycle time (min) 600 383 240 180 120 100 80 1 t1 address valid to - iord/ - iowr setup (min) 70 50 30 30 25 15 10 t2 - iord/ - iowr (min) 165 125 100 80 70 65 55 1 t2 - iord/ - iowr (min) register (8 bit) 290 290 290 80 70 65 55 1 t2i - iord/ - iowr recovery time (min) - - - 70 25 25 20 1 t3 - iowr data setup (min) 60 45 30 30 20 20 15 t4 - iowr data hold (min) 30 20 15 10 10 5 5 t5 - iord data setup (min) 50 35 20 20 20 15 10 t6 - iord data hold (min) 5 5 5 5 5 5 5 t6z - iord data tristate (max) 30 30 30 30 30 20 20 2 t7 address valid to - iocs16 assertion (max) 90 50 40 n/a n/a n/a n/a 4 t8 address valid to - iocs16 released (max) 60 45 30 n/a n/a n/a n/a 4 t9 - iord/ - iowr to address valid hold 20 15 10 10 10 10 10 trd read data valid to iordy active (min), if iordy initially low after ta 0 0 0 0 0 0 0 ta iordy setup time 35 35 35 35 35 na 5 na 5 3 tb iordy pulse width (max) 1250 1250 1250 1250 1250 na 5 na 5 tc iordy assertion to release (max) 5 5 5 5 5 na 5 na 5 notes: all timings are in nanoseconds. the maximum load on - iocs16 i s 1 lsttl with a 50 pf (40pf below 120nsec cycle time) total load. all times are in nanoseconds. minimum time from - iordy high to - iord high is 0 nsec, but minimum - iord width shall still be met. 1) t0 is the minimum total cycle time, t2 is the minimum com mand active time, and t2i is the minimum command recovery time or command inactive time. the actual cycle time equals the sum of the actual command active time and the actual command inactive time. the three timing requirements of t0, t2, and t2i shall be met. the minimum total cycle time requirement is greater than the sum of t2 and t2i. this means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device?s identify device dat a. a compactflash storage card implementation shall support any legal host implementation. 2) this parameter specifies the time from the negation edge of - iord to the time that the data bus is no longer driven by the compactflash storage card (tri - state). 3) the delay from the activation of - iord or - iowr until the state of iordy is first sampled. if iordy is inactive then the host shall wait until iordy is active before the pio cycle can be completed. if the compactflash storage card is not driving iordy n egated at ta after the activation of - iord or - iowr, then t5 shall be met and trd is not applicable. if the compactflash storage card is driving iordy negated at the time ta after the activation of - iord or - iowr, then trd shall be met and t5 is not applic able. 4) t7 and t8 apply only to modes 0, 1 and 2. for other modes, this signal is not valid. 5) iordy is not supported in this mode. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 35 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification figure 3 - 7 : true ide pio mode timing diagram all waveforms in this diagram are shown with the asserted state high. neg ative true signals appear inverted on the bus relative to the diagram. notes: 1) device address consists of - cs0, - cs1, and a[02::00] 2) data consists of d[15::00] (16 - bit) or d[07::00] (8 bit) 3) - iocs16 is shown for pio modes 0, 1 and 2. for other modes, this signal is ignored. 4) the negation of iordy by the device is used to extend the pio cycle. the determination of whether the cycle is to be extended is made by the host after ta from the assertion of - iord or - iowr. the assertion and negation of iordy is described in the following three cases: 4 - 1) device never negates iordy: no wait is generated. 4 - 2) device starts to drive iordy low before ta, but causes iordy to be asserted before ta: no wait generated. 4 - 3) device drives iordy low before ta: wait g enerated. the cycle completes after iordy is reasserted. for cycles where a wait is generated and - iord is asserted, the device shall place read data on d15 - d00 for trd before causing iordy to be asserted. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 36 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.12 true ide multiword dma mode read/write timing s pecification the timing diagram for true ide dma mode of operation in this section is drawn using the conventions in the ata - 4 specification, which are different than the conventions used in the pcmcia specification and earlier versions of this specificat ion. signals are shown with their asserted state as high regardless of whether the signal is actually negative or positive true. consequently, the - iord, the - iowr and the - iocs16 signals are shown in the diagram inverted from their electrical states on th e bus. table 3 - 1 7 : true ide multiword dma mode read/write timing item mode 0 (ns) mode 1 (ns) mode 2 (ns) mode 3 (ns) mode 4 (ns) note to cycle time (min) 480 150 120 100 80 1 td - iord / - iowr asserted width (min) 215 80 70 65 55 1 te - iord data access (max) 150 60 50 50 45 tf - iord data hold (min) 5 5 5 5 5 tg - iord/ - iowr data setup (min) 100 30 20 15 10 th - iowr data hold (min) 20 15 10 5 5 ti dmack to ? iord/ - iowr setup (min) 0 0 0 0 0 tj - iord / - iowr to - dmack hold (min) 20 5 5 5 5 tkr - iord negated width (min) 50 50 25 25 20 1 tkw - iowr negated width (min) 215 50 25 25 20 1 tlr - iord to dmarq delay (max) 120 40 35 35 35 tlw - iowr to dmarq delay (max) 40 40 35 35 35 tm cs(1:0) valid to ? iord / - iowr 50 30 25 10 5 tn cs(1:0) hold 15 10 10 10 10 tz - dmack 20 25 25 25 25 notes: 1) t0 is the minimum total cycle time and td is the minimum command active time, while tkr and tkw are the minimum command recovery time or command inactive time for input and output cycles respectively. the actual cycle time equals the sum of the actual command active time and the actual command inactive time. the three timing requirements of t0, td, tkr, and tkw shall be met. the minimum total cycle time requirement is greater than the sum of td and tkr or tkw.for input and output cycles respectively. this means a host implementation can lengthen either or both of td and either of tkr, and tkw as needed to ensure that t0 is equal to or greater than the value reported in the device?s identify device data. a compactflash storage card implementation shall support any legal host implementation. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 37 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification notes: (1) if the card cannot sustain continuous , minimum cycle time dma transfers, it may negate dmarq within the time specified from the start of a dma transfer cycle to suspend the dma transfers in progress and reassert the signal at a later time to continue the dma operation. (2) this signal may be negated by the host to suspend the dma transfer in progress. figure 3 - 8 : true ide multiword dma mode read/write timing diagram y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 38 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.3.13 ultra dma mode read/write timing specification ultra dma overview ultra dma is an optional data transfer protocol used with the read dma, and write dma, commands. when this protocol is enabled, the ultra dma protocol shall be used instead of the multiword dma protocol when these commands are issued by the host. this protocol applies to the ultra dma data burst only. when this protocol is used there are no changes to other elements of the ata protocol (e.g., command block register access). ultra dma operations can take place in any of the three basic interface modes: pc card memory mode, pc card i/o mod e, and true ide (the original mode to support udma). the usage of signals in each of the modes is shown in table 3- 18 :ultra dma signal usage in each interface mode table 3- 18 :ultra dma signal usage in each interface mode udma signal type pin # (non udm a mem mode) pc card mem mode udma pc card io mode udma true ide mode udma dmarq output 43 ( - inpack) - dmarq - dmarq dmarq dmack input 44 ( - reg) - dmack dmack - dmack stop input 35 ( - iowr) stop 1 stop 1 stop 1 hdmardy(r) hstrobe(w) input 34 ( - iord) - hdmardy(r) 1, 2hstrobe(w) 1, 3, 4 - hdmardy(r) 1, 2 hstrobe(w) 1, 3, 4 - hdmardy(r) 1, 2 hstrobe(w) 1, 3, 4 ddmardy(w) dstrobe(r) output 42 ( - wait) - ddmardy(w) 1, 3dstrobe(r) 1. 2. 4 - ddmardy(w) 1, 3 dstrobe(r) 1. 2. 4 - ddmardy(w) 1, 3 ds trobe(r) 1. 2. 4 data bidir ? (d[15:00]) d[15:00] d[15:00] d[15:00] address input ? (a[10:00]) a[10:00] a[10:00] a[02:00] 5 csel input 39 ( - csel) - csel - csel - csel intrq output 37 (ready) ready - intrq intrq card select input 7 ( - ce1) 31 ( - ce2) - ce1 - ce2 - ce1 - ce2 - cs0 - cs1 notes: 1) the udma interpretation of this signal is valid only during an ultra dma data burst. 2) the udma interpretation of this signal is valid only during and ultra dma data burst during a dma read command. 3) the udma interpretation of this signal is valid only during an ultra dma data burst during a dma write command. 4) the hstrobe and dstrobe signals are active on both the rising and the falling edge. 5) address lines 03 through 10 are not used in true ide mode. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 39 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification ultra dma data transfers timing table 3- 19 and table 3- 20 define the timings associated with all phases of ultra dma data bursts. table 3 - 19 : ultra dma data burst timing requirements name udma mode 0 udma mode 1 udma mode 2 udma mode 3 udma mode 4 udma mode 5 measure location 2 min max min max min max min max min max min max t2cycty p 240 160 120 90 60 40 sender tcyc 112 73 54 39 25 16.8 note 3 t2cyc 230 153 115 86 57 38 sender tds 15.0 10.0 7.0 7.0 5.0 4.0 recipient tdh 5.0 5.0 5.0 5.0 5.0 4.6 recipient tdvs 70.0 48.0 31.0 20.0 6.7 4.8 sender tdvh 6.2 6.2 6.2 6.2 6.2 4.8 sender tcs 15.0 10.0 7.0 7.0 5.0 5. 0 device tch 5.0 5.0 5.0 5.0 5.0 5.0 device tcvs 70.0 48.0 31.0 20.0 6.7 10.0 host tcvh 6.2 6.2 6.2 6.2 6.2 10.0 host tzfs 0 0 0 0 0 35 device tdzfs 70.0 48.0 31.0 20.0 6.7 25 sen der tfs 230 200 170 130 120 90 device tli 0 150 0 150 0 150 0 100 0 100 0 75 note 4 tmli 20 20 20 20 20 20 host tui 0 0 0 0 0 0 host taz 10 10 10 10 10 10 note 5 tzah 20 20 20 20 20 20 host tzad 0 0 0 0 0 0 device tenv 20 70 20 70 20 70 20 55 20 55 20 50 host trfs 75 70 60 60 60 50 sender trp 160 125 100 100 100 85 recipient tiordyz 20 20 20 20 20 20 device tziordy 0 0 0 0 0 0 device tack 20 20 20 20 20 20 host tss 50 50 50 50 50 50 sender notes: all timings in ns 1) all timing measurement switching points (low to high and high to low) shall be take n at 1.5 v. 2) all signal transitions for a timing parameter shall be measured at the connector specified in the measurement y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 40 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification location column. for example, in the case of trfs, both strobe and - dmardy transitions are measured at the sender connector. 3) t he parameter t cyc shall be measured at the recipient?s connector farthest from the sender. 4) the parameter t li shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respecti vely. both the incoming signal and the outgoing response shall be measured at the same connector. 5) the parameter taz shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus to allow for a bus turnar ound. 6) see the ac timing requirements in table 3 - 2 1 : ultra dma ac signal requirements. table 3- 20 : ultra dma data burst timing descriptions name comment notes t2cyctyp typical sustained average two cycle time tcyc cycle time allowing for a symmetry and clock variations (from strobe edge to strobe edge) t2cyc two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of strobe) tds data setup time at recipient (from dat a valid until strobe edge) 2, 5 tdh data hold time at recipient (from strobe edge until data may become invalid) 2, 5 tdvs data valid setup time at sender (from data valid until strobe edge) 3 tdvh data valid hold time at sender (from strobe ed ge until data may become invalid) 3 tcs crc word setup time at device 2 tch crc word hold time device 2 tcvs crc word valid setup time at host (from crc valid until - dmack negation) 3 tcvh crc word valid hold time at sender (from - dmack neg ation until crc may become invalid) 3 tzfs time from strobe output released - to - driving until the first transition of critical timing. tdzfs time from data output released - to - driving until the first transition of critical timing. tfs first strob e time (for device to first negate dstrobe from stop during a data in burst) tli limited interlock time 1 tmli interlock time with minimum 1 tui unlimited interlock time 1 taz maximum time allowed for output drivers to release (from asserted or negated) y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 41 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification name comment notes tzah minimum delay time required for output tzad drivers to assert or negate (from released) tenv envelope time (from - dmack to stop and - hdmardy during data in burst initiation and from dmack to stop during data out burst initiation) trfs ready - to - final - strobe time (no strobe edges shall be sent this long after negation of - dmardy) trp ready - to - pause time (that recipient shall wait to pause after negating - dmardy) tiordyz maximum time before relea sing iordy 6 tziordy minimum time before driving iordy 4, 6 tack setup and hold times for - dmack (before assertion or negation) tss time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) notes: 1) the parameters t ui , t mli (in figure 3 - 12 : ultra dma data - in burst device termination timing and figure 3 - 13: ultra dma data - in burst host termination timing), and tli indicate sender - to - recipient or recipient - to - sender interlocks,i.e., one agent (either se nder or recipient) is waiting for the other agent to respond with a signal before proceeding. t ui is an unlimited interlock that has no maximum time value. t mli is a limited time - out that has a defined minimum. tli is a limited time - out that has a defin ed maximum. 2) 80 - conductor cabling (see 4.3.8.4) shall be required in order to meet setup (tds, tcs) and hold (tdh, tch) times inmodes greater than 2. 3) timing for t dvs , t dvh , t cvs and t cvh shall be met for lumped capacitive loads of 15 and 40 pf at the connector where the data and strobe signals have the same capacitive load value. due to reflections on the cable, these timing measurements are not valid in a normally functioning system. 4) for all timing modes the parameter tziordy may be greater than t env due to the fact that the host has a pull - up on iordy - giving it a known state when released. 5) the parameters t ds , and t dh for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end o f the cable. this could result in the minimum values for t ds and t dh for mode 5 at the middle connector being 3.0 and 3.9 ns respectively. 6) this parameter applies to true ide mode operation only. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 42 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification table 3 - 21 : ultra dma sender and recipient ic timing requirements name udma mode 0 (ns) udma mode 1 (ns) udma mode 2 (ns) udma mode 3 (ns) udma mode4 (ns) udma mode 5 (ns) min max min max min max min max min max min max tdsic 14.7 9.7 6.8 6.8 4.8 2.3 tdhic 4.8 4.8 4. 8 4.8 4.8 2.8 tdvsic 72.9 50.9 33.9 22.6 9.5 6.0 tdvhic 9.0 9.0 9.0 9.0 9.0 6.0 tdsic recipient ic data setup time (from data valid until strobe edge) (see note 2) tdhic recipient ic data hold time (from strobe edge until data may become invalid) (see note 2) tdvsic sender ic data valid setup time (from data valid until strobe edge) (see note 3) tdvhic sender ic data valid hold time (from strobe edge until data may become invalid) (see note 3) notes: 1) all t iming measurement switching points(low to high and high to low) shall be taken at 1.5 v. 2) the correct data value shall be captured by the recipient given input data with a slew rate of 0.4 v/ns rising and fal ing and the input strobe with a slew rate of 0.4 v/ns rising and falling at tdsic and tdhic timing (as measured through 1.5 v). 3) the parameters tdvsic and tdvhic shall be met for lumped capacitive loads of 15 and 40 pf at the ic where all signals have the same capacitive load value. noise that may couple onto the output signals from external sources has not been included in these values. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 43 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification initiating an ultra dma data - in burst all waveforms in this diagram are shown with the asserted state high. negative true signals appear inverted on the bus r elative to the diagram. notes: the definitions for the iordy: - ddmardy:dstrobe, - iord: - hdmardy:hstrobe, and - iowr:stop signal lines are not in effect until dmarq and - dmack are asserted. a[02:00], - cs0 & - cs1 are true ide mode signal definitions. a[10:0 0], - ce1 and - ce2 are pc card mode signals. the bus polarity of ( - )dmack and ( - )dmarq are dependent on interface mode active. figure 3 - 9 : ultra dma data - in burst initiation timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 44 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification sustaining an ultra dma data - in burst all waveforms in this diagram are shown with the asserted state high. negative true signals appear inverted on the bus relative to the diagram. notes: d[15:00] and dstrobe signals are shown at both the host and the device to emphasize that cable settling time as well as cable propaga tion delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. figure 3 - 10 : sustained ultra dma data - in burst timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 45 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification host pausing an ultra dma data - in burst all waveforms in this diagram are shown with the asserted state high. negative true signals appear inverted on the bus relative to the diagram. notes: 1) the host may assert stop to request termination of the ultra dma data burst no sooner than t rp aft er - hdmardy is negated. 2) after negating - hdmardy, the host may receive zero, one, two, or three more data words from the device. 3) the bus polarity of the ( - ) dmarq and ( - )dmack signals is dependent on the active interface mode. figure 3 - 11 : ultra dma data - in burst host pause timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 46 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification device terminating an ultra dma data - in burst all waveforms in this diagram are shown with the asserted state high.negative true signals appear inverted on the bus relative to he diagram. notes: the definitions for the stop, hdmardy, and dstrobe signal lines are no longer in effect after dmarq and dmack are negated. a[02:00], - cs0 & - cs1 are true ide mode signal definitions. a[10:00], - ce1 and - ce2 are pc card mode signals. the bus polarity of d marq and dmack are dependent on the active interface mode. figure 3 - 12 : ultra dma data - in burst device termination timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 47 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification host terminating an ultra dma data - in burst all waveforms in this diagram are shown with the asserted state high. neg ative true signals appear inverted on the bus relative to the diagram. notes: the definitions for the stop, hdmardy, and dstrobe signal lines are no longer in effect after dmarq and dmack are negated. a[02:00], - cs0 & - cs1 are true ide mode signal definit ions. a[10:00], - ce1 and - ce2 are pc card mode signal definitions. the bus polarity of dmarq and dmack depend on the active interface mode. figure 3- 13 : ultra dma data - in burst host termination timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 48 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification initiating an ultra dma data - out burst all waveforms in this diagram are shown with the asserted state high.negative true signals appear inverted on the bus relative to the diagram. note: the definitions for the stop, ddmardy, and hstrobe signal lines are not in effect until dmarq and dmack are asserted. a[02:00], - cs0 & - cs1 are true ide mode signal definitions. a[10:00], - ce1 and - ce2 are pc card mode signal definitions. the bus polarity of dmarq and dmack depend on the active interface mode. figure 3- 14 : ultra dma data - out burst initiati on timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 49 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification sustaining an ultra dma data - out burst all waveforms in this diagram are shown with the asserted state high.negative true signals appear inverted on the bus relative to the diagram. note: data (d[15:00]) and hstrobe signals are sho wn at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not al ow the data signals to be considered stable at the device until some time after they are driven by the host. figure 3- 15 : sustained ultra dma data - out burst timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 50 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification device pausing an ultra dma data - out burst all waveforms in this diagram are shown with the asserted state high. negative true signals appear inverted on the bus relative to the diagram. notes: 1) the device may negat e dmarq to request termination of the ultra dma data burst no sooner than t rp after - ddmardy is negated. 2) after negating - ddmardy, the device may receive zero, one, two, or three more data words from the host. 3) the bus polarity of dmarq and dmack depen d on the active interface mode. figure 3- 16 : ultra dma data - out burst device pause timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 51 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification device terminating an ultra dma data - out burst all waveforms in this diagram are shown with the asserted state high. negative true signals appear inverted on the bus relative to the diagram. note: the definitions for the stop, ddmardy, and hstrobe signal lines are no longer in effect afterdmarq and dmack are negated. a00 - a02, - cs0 & - cs1 are true ide mode signal definitions. a00 - a10, - ce1 and - ce2 are pc car d mode signals. the bus polarity of dmarq and dmack depend on the active interface mode. figure 3 1 y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 52 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification host terminating an ultra dma data - out burst all waveforms in this diagram are shown with the asserted state high. negative true signals appear inverted on the bus relative to he diagram. notes: the definitions for the stop, ddmardy, and hstrobe signal lines are no longer in effect after dmarq and dmack are negated. a[02:00], - cs0 & - cs1 are true ide mode signal definitions. a[10:00], - ce1 and - ce2 are pc card mode signal definitions. the bus polarity of dmarq and dmack depend on the active interface mode. figure 3- 18 : ultra dma data - out burst host termination timing y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 53 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification ultra dma crc calcu lation table 3- 22 : equations for parallel generation of an ultra dma crc crcin0 = f16 crcin8 = f8 xor f13 crcin1 = f15 crcin9 = f7 xor f12 crcin2 = f14 crcin10 = f6 xor f11 crcin3 = f13 crcin11 = f5 xor f10 crcin4 = f12 crcin12 = f4 xor f9 x or f16 crcin5 = f11 xor f16 crcin13 = f3 xor f8 xor f15 crcin6 = f10 xor f15 crcin14 = f2 xor f7 xor f14 crcin7 = f9 xor f14 crcin15 = f1 xor f6 xor f13 f1 = d00 xor crcout15 f9 = d08 xor crcout7 xor f5 f2 = d01 xor crcout14 f10 = d09 xor cr cout6 xor f6 f3 = d02 xor crcout13 f11 = d10 xor crcout5 xor f7 f4 = d03 xor crcout12 f12 = d11 xor crcout4 xor f1 xor f8 f5 = d04 xor crcout11 xor f1 f13 = d12 xor crcout3 xor f2 xor f9 f6 = d05 xor crcout10 xor f2 f14 = d13 xor crcout2 xor f3 xor f10 f7 = d06 xor crcout9 xor f3 f15 = d14 xor crcout1 xor f4 xor f11 f8 = d07 xor crcout8 xor f4 f16 = d15 xor crcout0 xor f5 xor f12 notes: 1) f=feedback 2) d[15:0] = data to or from the bus 3) crcout = 16 - bit edge triggered result (current crc) 4) crcout[15:0] are sent on matching order bits of d[15:00] an example of a crc generator implementation is provided below in figure 3 - 19 : ultra dma parallel crc generator example. figure 3- 19 : ultra dma parallel crc generator example y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 54 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.4 card config uration the compactflash storage cards are identified by appropriate information in the card information structure (cis). the following configuration registers are used to coordinate the i/o spaces and the interrupt level of cards that are located in the system. in addition, these registers provide a method for accessing status information about the compactflash storage card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that ap pears on dedicated pins in memory cards that have alternate use in i/o cards. 3.4.1 compactflash storage card registers and memory space decoding table 3 - 23: compactflash storage card registers and memory space decoding - ce2 - ce1 - reg - oe - we a10 a9 a8 - a4 a3 a 2 a1 a 0 selected space 1 1 x x x x x xx x x x x standby and udma transfer x 0 0 0 1 0 1 xx x x x 0 configuration registers read 1 0 1 0 1 x x xx x x x x common memory read (8 bit d7 - d0) 0 1 1 0 1 x x xx x x x x common memory read (8 bit d15 - d8) 0 0 1 0 1 x x xx x x x 0 common memory read (16 bit d15 - d0) x 0 0 1 0 0 1 xx x x x 0 configuration registers write 1 0 1 1 0 x x xx x x x x common memory write (8 bit d7 - d0) 0 1 1 1 0 x x xx x x x x common memory write (8 bit d15 - d8) 0 0 1 1 0 x x xx x x x 0 common memory write (16 bit d15 - d0) x 0 0 0 1 0 0 xx x x x 0 card information structure read 1 0 0 1 0 0 0 xx x x x 0 invalid access (cis write) 1 0 0 0 1 x x xx x x x 1 invalid access (odd attribute read) 1 0 0 1 0 x x xx x x x 1 invalid access (odd attribute write) 0 1 0 0 1 x x xx x x x x invalid access (odd attribute re ad) 0 1 0 1 0 x x xx x x x x invalid access (odd attribute write) y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 55 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification table 3- 24: pc card memory mode udma function - ce2 - ce1 - dmarq - inpack - dmack - reg stop - iowr - dmardy - iord (r) - wait (w) strobe - wait (r) - iord (w) dma cmd a10 - a00 operation 1 1 1 x x x x no xx standby x x 0 1 x x 1 yes xx device udma transfer request (assert dmarq) x x 0 1 1 x 1 yes xx host acknowledge preparation 1 1 0 1 1 1 1 yes static host acknowledge preparation 1 1 0 0 1 1 1 yes static dma acknowledge (stopped) 1 1 0 0 0 0 1 yes static burst initiation / active 1 1 0 0 0 x / or \ yes static burst transfer 1 1 0 0 0 1 0 or 1 rd static data in burst host pause 1 1 0 0 0 0 0 or 1 rd static data in burst device pause 1 1 0 0 0 1 0 or 1 wr static data out burst device pause 1 1 0 0 0 0 0 or 1 wr static data out burst host pause 1 1 1 0 0 0 0 or 1 rd static device initiat ing burst termination 1 1 1 0 1 1 0 or 1 rd static host acknowledgement of device initiated burst termination 1 1 0 0 1 0 0 or 1 yes static host initiating burst termination 1 1 1 0 1 1 0 or 1 yes static device acknowledgin g host initiated burst termination 1 1 1 0 1 1 / yes static device aligning strobe to asserted before crc transfer 1 1 1 / 1 1 1 yes static crc data transfer for udma burst 1 1 1 1 1 1 1 yes static burst completed table 3- 25 : compactflash storage card configuration registers decoding - ce2 - ce1 - reg - oe - we a10 a9 a8 - a4 a3 a2 a1 a0 selected register x 0 0 0 1 0 1 00 0 0 0 0 configuration option reg read x 0 0 1 0 0 1 00 0 0 0 0 con figuration option reg write x 0 0 0 1 0 1 00 0 0 1 0 card status register read x 0 0 1 0 0 1 00 0 0 1 0 card status register write x 0 0 0 1 0 1 00 0 1 0 0 pin replacement register read x 0 0 1 0 0 1 00 0 1 0 0 pin replacement register write x 0 0 0 1 0 1 00 0 1 1 0 socket and copy register read x 0 0 1 0 0 1 00 0 1 1 0 socket and copy register write y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 56 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.4.2 attribute memory function attribute memory is a space where co mpactflash storage card identification and configuration information are stored, and is limited to 8 bit wide accesses only at even addresses. the card configuration registers are also located here. for compactflash storage cards, the base address of the c ard configuration registers is 200h. for the attribute memory read function, signals - reg and - oe shall be active and - we inactive during the cycle. as in the main memory read functions, the signals - ce1 and - ce2 control the even - byte and odd - byte address, but only the even- byte data is valid during the attribute memory access. refer to table 3- 26 : attribute memory function below for signal states and bus validity for the attribute memory function. table 3 - 26 : attribute memory function function mode dma cmd - reg - ce2 - ce1 a10 a9 a0 - oe - we d15 - d8 d7 - d0 standby mode don?t care h h h x x x x x high z high z standby mode no x h h x x x x x high z high z udma operation: ultra dma mode read/write timing specification) yes l 1 h h x x x h h odd byte even byte read byte access cis rom (8 bits) no l h l 2 l l l l 2 h high z even byte write byte access cis (8 bits) (invalid) no l h l2 l l l h l 2 don?t care even byte read byte access configura tion compactflash storage (8 bits) no l h l l h l l h high z even byte write byte access configuration compactflash storage (8 bits) no l h l l h l h l don?t care even byte read byte access configuration cf+ (8 bits) no l h l x x l l h high z even byte write byte access configuration cf+ (8 bits) no l h l x x l h l don?t care even byte read word access cis (16 bits) no l l 2 l 2 l l x l 2 h not valid even byte write word access cis (16 bits) (inva lid) no l l 2 l 2 l l x h l 2 don?t care even byte read word access configuration compactflash storage (16 bits) no l l 2 l 2 l h x l2 h not valid even byte write word access configuration compactflash storage (16 bits) no l l 2 l 2 l h x h l 2 don?t care even byte read word access configuration cf+ (16 bits) no l l 2 l 2 x x x l 2 h not valid even byte write word access configuration cf+ (16 bits) no l l 2 l 2 x x x h l 2 don?t care even byte note: 1) in udma op eration, the - reg ( - dmack) signal shall be asserted only in response to - dmarq. 2) the - ce signal or both the - oe signal and the - we signal shall be de - asserted between consecutive cycle operations. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 57 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.4.3 configuration option register (base + 00h in attribute memor y) the configuration option register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the compactflash card. operation d7 d6 d5 d4 d3 d2 d1 d0 r/w sreset levlreq conf5 conf4 conf3 conf2 conf1 conf0 figure 3 - 20 : configuration option register note: conf5 and conf4 are written as zero (0). table 3 - 27: compactflash card configurations conf5 conf4 conf3 conf2 conf1 conf0 disk card mode 0 0 0 0 0 0 memory mapped 0 0 0 0 0 1 i/o ma pped, any 16 byte system decoded boundary 0 0 0 0 1 0 i/o mapped, 1f0h - 1f7h/3f6h - 3f7h 0 0 0 0 1 1 i/o mapped, 170h - 177h/376h - 377h 3.4.4 card configuration and status register (base + 02h in attribute memory) the card configuration and status register contains information about the card?s condition . operation d7 d6 d5 d4 d3 d2 d1 d0 read changed sigchg iois8 - xe audio pwrdwn int 0 write 0 sigchg iois8 - xe audio pwrdwn 0 0 figure 3 - 21 : card configuration and status register 3.4.5 pin replaceme nt register (base + 04h in attribute memory) operation d7 d6 d5 d4 d3 d2 d1 d0 read 0 0 cready cwprot 1 1 rready wprot write 0 0 cready cwprot 0 0 mready mwprot figure 3 - 22 : pin replacement register y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 58 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification table 3 - 28 : pin replacement changed bit/mask bit v alues initial value of (c) status written by host final comments ?c? bit ?m? bit ?c? bit 0 x 0 0 unchanged 1 x 0 1 unchanged x 0 1 0 cleared by host x 1 1 1 set by host 3.4.6 socket and copy register (base + 06h in attribute memory) this register contains additional configuration information. this register is always written by the system before writing the card?s configuration index register. operation d7 d6 d5 d4 d3 d2 d1 d0 read reserved 0 0 obsolete1(drive#) 0 0 0 0 writ e 0 0 0 obsolete1(drive#) x x x x figure 3 - 23 : socket and copy register y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 59 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.5 i/o transfer function the i/o transfer to or from the compactflash storage can be either 8 or 16 bits. when a 16 bit accessible port is addressed, the signal - iois16 is asserted by the compactflash card . otherwise, the - iois16 signal is de - asserted. when a 16 bit transfer is attempted, and the - iois16 signal is not asserted by the compactflash card, the system shall generate a pair of 8 bit references to acces s the word?s even byte and odd byte. the compactflash card permits both 8 and 16 bit accesses to all of its i/o addresses, so - iois16 is asserted for all addresses to which the compactflash card responds. the compactflash card may request the host to ext end the length of an input cycle until data is ready by asserting the - wait signal at the start of the cycle. table 3 - 29 : pcmcia mode i/o function function code - reg - ce2 - ce1 a0 - iord - iowr d15 - d8 d7 - d0 standby mode x h h x x x high z h igh z byte input access (8 bits) l l h h l l l h l l h h high z high z even - byte odd - byte byte output access (8 bits) l l h h l l l h h h l l don?t care don?t care even - byte odd - byte word input access (16 bits) l l l l l h odd - byte even - byte word output access (16 bits) l l l l h l odd - byte even - byte i/o read inhibit h x x x l h don?t care don?t care i/o write inhibit h x x x h l high z high z high byte input only (8 bits) l l h x l h odd - byte high z high byte output only (8 bits) l l h x h l odd - byte don?t care y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 60 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.6 common memory transfer function the common memory transfer to or from the compactflash storage can be either 8 or 16 bits. the compactflash storage card permits b oth 8 and 16 bit accesses to all of its common memory addresses. the compactflash storage card may request the host to extend the length of a memory write cycle or extend the length of a memory read cycle until data is ready by asserting the - wait signal a t the start of the cycle. table 3 - 30 : common memory function function code - reg - ce2 - ce1 a0 - oe - we d15 - d8 d7 - d0 standby mode x h h x x x high z high z byte read access (8 bits) h h h h l l l h l l h h high z high z even - byt e odd - byte byte write access (8 bits) h h h h l l l h h h l l don?t care don?t care even - byte odd - byte word read access (16 bits) h l l x l h odd - byte even - byte word write access (16 bits) h l l x h l odd - byte even - byte odd byte read only (8 bits) h l h x l h odd - byte high z odd byte write only (8 bits) h l h x h l odd - byte don?t care 3.7 true ide mode i/o transfer function y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 61 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification the compactflash storage card can be configured in a true ide mode o f operation. the compactflash storage card is configured in this mode only when the - oe input signal is grounded by the host during the power off to power on cycle. compactflash storage cards support the following optional detection methods: 1. the card is permitted to monitor the ? oe ( - ata sel) signal at any time(s) and switch to pcmcia mode upon detecting a high level on the pin. 2. the card is permitted to re - arbitrate the interface mode determination following a transition of the ( - )reset pin. 3. the ca rd is permitted to monitor the ? oe ( - ata sel) signal at any time(s) and switch to true ide mode upon detection of a continuous low level on pin for an extended period of time. host implementers should not rely on any of these optional detection methods in their designs. in the true ide mode, the pcmcia protocol and configuration are disabled and only i/o operations to the task file and data register are allowed. in this mode, no memory or attribute registers are accessible to the host. compactflash storage cards permit 8 bit pio mode data accesses if the user issues a set feature command to put the compactflash storage card in 8 bit mode. note: removing and reinserting the compactflash storage card while the host computer?s power is on will reconfigure th e compactflash storage card to pc card ata mode from the original true ide mode. to configure the compactflash storage card in true ide mode, the 50 - pin socket is power cycled with the compactflash storage card inserted and - oe (output enable) asserted. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 62 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification table 3 - 31 : true ide mode i/o function function code - cs1 - cs0 a0 - a2 - dmack - iord - iowr d15 - d8 d7 - d0 invalid modes l l x x x x undefined in/out undefined in/out l x x l l x undefined out undefined out l x x l x l undefined in undefined in x l x l l x undefined out undefined out x l x l x l undefined in undefined in standby mode h h x h x x high z high z task file write h l 1- 7h h h l don?t care data in task file read h l 1- 7h h l h high z data out pio data register write h l 0 h h l odd - b yte in even - byte in dma data register write h h x l h l odd - byte in even - byte in pio data register read h l 0 h l h odd - byte out even - byte out dma data register read h h x l l h odd - byte out even - byte out control register write l h 6h h h l don?t care control in alt status read l h 6h h l h high z status out drive address1 l h 7h h l h high z data out notes: 1) implemented for backward compatibility. bit d7 of the register shall remain high z to prevent conflict with any floppy disk controller at the s ame address. the host software should not rely on the contents of this register. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 63 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 3.8 host configuration requirements for master/slave or new timing modes the cf advanced timing modes include pcmcia style i/o modes that are faster than the original 250 ns cycle time. these modes are not supported by the pcmcia specification nor cf by cards based on revisions of the cf specification before revision 3.0. hosts shall ensure that all cards accessed through a common electrical interface are capable of operation at the desired, faster than 250 ns, i/o mode before configuring the interface for that i/o mode. advanced timing modes are pcmcia style i/o modes that are 100 ns or faster, pcmcia memory modes that are 100ns or faster, true ide pio modes 5,6 and multiword dma modes 3,4. these modes are permitted to be used only when a single card is present and the host and card are connected directly, without a cable exceeding 0.15m in length. consequently, the host shall not configure a card into an advanced timing mode if two cards are sharing i/o lines, as in master/slave operation, nor if it is constructed such that a cable exceeding 0.15 meters is required to connect the host to the card. the load presented to the host by cards supporting ultra dma is more controlled than that presented by other compactflash cards. therefore, the use of a card that does not support ultra dma in a master/slave arrangement with a ultra dma card can affect the critical timing of the ultra dma transfers. the host shall not configure a car d into ultra dma mode when a card not supporting ultra dma is also present on the same interface when the use of two cards on an interface is otherwise permitted, the host may use any mode that is supported by both cards, but to achieve maximum performanc e it should use its highest performance mode that is also supported by both cards. 3.9 termination r esistors for ultra dma operation y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 64 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification atp industrial grade cf cards provide embedded termination resistors for operation in any of the ultra dma modes. the following table describes typical values for series termination at the cf card . table 3 - 2: termination r esistors for ultra dma operation signal termination - iord ( - hdmardy, hstrobe) 82 ohm - iowr (stop) 82 ohm - cs0, - cs1 82 ohm a00, a0 1, a02 82 ohm - dmack 82 ohm d15 through d00 33 ohm dmarq 22 ohm intrq 22 ohm iordy ( - ddmardy, dstrobe) 22 ohm - reset 82 ohm 4 s .m .a .r.t . function y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 65 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification 4.1 s. m . a . r . t . feature self - monitoring analysis and reporting technology (s.m.a.r. t.) is used to protect the user from unscheduled downtime. by monitoring and storing critical performance and calibration parameters, s .m .a .r .t . feature set devices attempt to predict the likelihood of near - term degradation or fault condition. informing th e host system of a negative reliability condition allows the host system to warn the user of the impending risk of a data loss and advise the user of appropriate action. 4.2 s. m . a . r . t . feature register values in order to select a subcommand the host must write the subcommand code to the device's features register before issuing the s .m .a .r .t . function set command. the subcommands are listed below. table 4 - 2 : s . m . a . r . t . feature register values command command code s.m.a.r.t. read data d0h s.m.a.r.t. re ad attribute threshold d1h s.m.a.r.t. enable/disable autosave d2h s.m.a.r.t. save attribute values d3h s.m.a.r.t. execute off - line immidiate d4h reserved d5h reserved d6h s.m.a.r.t. enable operations d8h s.m.a.r.t. disable operations d9h s.m.a.r.t. return status dah n ote: if the reserved size is below a threshold, status can be read from the cylinder register using the return status command (dah) 4.3 s. m . a . r . t . data structure the following 512 bytes make up the device s.m.a.r.t. data structure. users can obtain the data y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 66 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification using the ?read data? command (d0h). table 4 - 3 : s.m.a.r.t. data structure byte f/v description 0~1 x revision code 115 ~116 v power cycle count of the device 362 v off - line data collection status 363 x self - test execution sta tus byte 364~ 365 v total time in seconds to complete off - line data collection activity 367 f off - line data collection capability 368~ 369 f s.m.a.r.t. capability 370 f error logging capability 7 - 1 reserved 0 1 = device error logging supported 372 f short self - test routine recommended polling time(in minutes) 373 f extended self - test routine recommended polling time(in minutes) 374 f conveyance self - test routine recommended polling time(in minutes) 375~385 r reserved 386~395 f firmware version/date code 396~397 f number of initial invalid block (396=msb, 397=lsb) 398~399 v number of run time bad block (398=msb, 399=lsb) 400 v number of spare block 401 ~40 2 v erase count ( low word. th e value is identical to that of byte 409~410) 403 ~405 f ?smi ? 406 f number of max pair 407~41 0 v erase count ( 407~408 =high word, 409~410 =low word) 511 v data structure checksum notes: f=content (byte ) is fixed and does not change v=content (byte ) is variable and maybe change depending on the state of the device or the command executed by the device x= content ( byte) is vendor specific and maybe fixed or variable r= content ( byte ) is reserved and shall be zero n=nth management unit *4 byte value: [msb] [2][1][lsb ] 4.4 atp s.m.a.r.t. tool atp provides s.m.a.r.t. tool for windows 2000/xp/vista/7 and linux, it can monitor the state of industrial grad compactflash, and the following picture shows s.m.a.r.t. tool operation. t his tool y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 67 atp confidential & proprietary
revision 3.6 atp i ndustrial grade compactflash card specification support s that users read s pare and bad block information. users can thus evaluate drive health at run time and receive an early warning before the drive life ends. note: please contact atp sales or visit atp website for the updated atp s.m.a.r.t. tool version. y y o o u u r r u u l l t t i i m m a a t t e e m m e e m m o o r r y y s s o o l l u u t t i i o o n n ! ! 68 atp confidential & proprietary

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